It is well known that the drive currents of metal-oxide-semiconductor (MOS) devices are affected by the stresses applied on the channel regions of the MOS devices. The stresses in the channel regions may improve the carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction (channel length direction) and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in the channel length direction.
Although the beneficial stresses in the channel regions are generally desirable, it is also realized that the magnitudes of the drive current improvement is related to the magnitudes of the stresses. On a same semiconductor chip, the MOS devices may be applied with stresses having different magnitudes. Accordingly, the drive current improvements for different MOS devices may be different, resulting in non-uniform drive currents, hence drive current drift.
It is preferred that the performances of MOS devices are predictable, so that at circuit design time, simulations that accurately reflect the circuit behavior may be performed. Accordingly, it is preferred that in a semiconductor chip, MOS devices of a same type and in a same type of circuits have a uniform performance. However, with the drive current drift, during the simulations of the circuit design, the drive current drift has to be compensated for. What makes the compensation of the drive current drift complicated is that the stresses of MOS device are affected by various factors and those factors behave differently for different layouts. Accordingly, new methods for reducing the drive current drift of MOS devices are needed.